In a bus-powered communication system, polarity communication is traditionally used. The structure of such communication mode is shown in FIG. 1. The polarity scheme needs to use a marked twisted pair as signal lines for connecting while preventing connection errors. That is to say, the polarity of the signal lines BUS_C and GND_C in FIG. 1 must be fixed. This mode has the following disadvantages that it is easy to reverse the signal lines during line wiring such that it is impossible for the signal to transmit normally. In addition, there are many inconveniences in polarity connection during line inspection and correction process. Based on the above reasons, bus communication systems now begin to use non-polarity connections.
As shown in FIG. 2, a scheme for implementing a bus non-polarity connection by using a rectifier bridge circuit is shown. The rectifier bridge is composed of four diodes D1, D2, D3 and D4. BUS_C and GND_C are two port bus signals output by a master device, while BUS and GND are bus signals following a rectifier bridge. The unidirectional conduction characteristic of a diode can ensure that polarities of BUS and GND following the rectifier bridge are fixed when positive and negative polarities of BUS_C and GND_C change.
Due to the unidirectional conduction characteristics of diodes in the rectifier bridge, when the master device sends an instruction by a bus voltage fall, there is no effective discharge path in a circuit following the rectifier bridge. So, the signal BUS may have problems in signal integrity. As shown in FIG. 3, when the master device sends an instruction, the bus voltage will fall from 24V to 5V, but there is no effective discharge path, and the bus voltage following the rectifier bridge may only fall to about 12V, and the signal quality is poor. At this time, it is impossible for the slave device to accurately monitor the instruction sent on the bus, thereby causing the system to work abnormally.
The related art improves the above problems existing in non-polarity connections mainly by adding a series resistor to the bus so as to form a discharge path. However, this technology has the disadvantages of large power consumption, unsatisfactory discharge effect, and affecting bus communication performance.
The present disclosure proposes a bus discharge circuit integrated inside the chip. The discharge path is triggered only when the bus voltage falling edge is detected by the circuit, and the discharge time, discharge current and discharge trigger condition can be configured, which effectively reduces the system power consumption and increases flexibility of functions. At the same time, the discharge circuit and a circuit module sensitive to noise are independent from each other, thereby not affecting normal operation of the system. Thus, the problem of poor adaptability existing in traditional technologies is avoided, and the flexibility of functions can be enhanced, such that it can be applied to more bus communication systems.
The related art mainly improves the quality of the transmitted signal mainly by adding a discharge path to a signal line following the rectifier bridge with a series resistor. The implementation manner is shown in FIG. 4. The circuit generates a path between the bus voltage following the rectifier bridge and a power supply VDD of the slave device function module by using a resistor Rx. When the bus voltage falls, the bus can discharge to VDD through Rx. This can avoid the problem that the bus voltage level cannot be matched with the communication protocol during communication, which would otherwise result in that the system operates abnormally.
In summary, the related art includes the following three major problems:
First, in order to obtain suitable discharge performance, the discharge resistor Rx needs to be designed and adjusted to obtain a sufficiently large discharge current. However, this path will always be open and the current is relatively large, which will greatly increase the power consumption of the system.
Second, signal noise existing in the bus will be coupled to VDD through the resistor Rx, such that VDD will become an unclean power supply. This will affect the performance of the signal processing circuit. In order to avoid this problem, it is necessary to add a filter circuit to VDD, which will increase the complexity of the power system and reduce the reliability of the system, and to this end, design cost will be increased.
Third, parameters such as the discharge current and discharge time of the circuit are fixed and cannot adapt to the requirements of different bus communication methods, and the application range is relatively narrow.